SystemVerilog probes · 60Vivado: supported

a function with a ref argument: function automatic void inc(ref logic [3:0] x)

Vivado: supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Pass by reference: Supported', 'Return values and void functions: Supported'

What does the open-source chain do with it?

iverilog: 'sorry: Reference ports not supported yet.' (design.sv:2); dewfpga bit stops before yosys, since #5 with the code: 'design.sv:2: ERROR [ref-argument]: function inc takes an argument by reference (ref logic [3:0] x): yosys does not read ref, and yosys-slang drops it, so the variable it is called with would never change on the board. Fix: pass the value in and return it (function automatic logic [3:0] inc(input logic [3:0] x); ... return x + 1; and v = inc(v);).'

Which error pages explain the messages?

• ref-argument: A function or task argument passed by reference; yosys' reader stops on it and yosys-slang builds the call as nothing.

What is the probe's code?

From test/sv/60_pass_by_ref.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  function automatic void inc(ref logic [3:0] x);   // pass by reference: the caller's variable changes
    x = x + 4'd1;
  endfunction
  logic [3:0] v;
  always_comb begin
    v = sw[3:0];
    inc(v);
    led = {12'd0, v};
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {i[7:4], 8'h5a, i[3:0]}; #1
      if (!(led === {12'd0, 4'(sw[3:0] + 4'd1)})) begin $display("FAIL: inc(v) through ref (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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