SystemVerilog probes · 61Vivado: supported

enum ranges: typedef enum {S[3]} (S0, S1, S2) and {T[5:7]} (T5, T6, T7)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Enumerated type ranges: Supported'

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 2 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/61_enum_range.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  typedef enum logic [1:0] {S[3]} s_t;        // an enum range: S0, S1, S2 (values 0, 1, 2)
  typedef enum logic [2:0] {T[5:7]} t_t;      // T5, T6, T7 (values 0, 1, 2)
  s_t s; t_t t;
  always_comb
    case (sw[1:0])
      2'd0:    s = S2;
      2'd1:    s = S0;
      default: s = S1;
    endcase
  always_comb
    if (sw[2]) t = T7;
    else       t = T6;
  assign led = {11'd0, t, s};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i; reg [1:0] s; reg [2:0] t;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 8; i = i + 1) begin
      sw = {13'h1abc, i[2:0]}; #1
      s = (sw[1:0] == 2'd0) ? 2'd2 : (sw[1:0] == 2'd1) ? 2'd0 : 2'd1;
      t = sw[2] ? 3'd2 : 3'd1;
      if (!(led === {11'd0, t, s})) begin $display("FAIL: S0..S2 and T5..T7 values (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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