errors · bitdewfpga bit, the source scan before the tools run

design.sv:2: ERROR [ref-argument]: function inc takes an argument by reference (ref logic [3:0] x): yosys does not read ref, and yosys-slang drops it, so the variable it is called with would never change on the board. Fix: pass the value in and return it (function automatic logic [3:0] inc(input logic [3:0] x); ... return x + 1; and v = inc(v);).

dewfpga sim stops before it too, iverilog saying sorry: Reference ports not supported yet.

design.sv:2: ERROR [ref-argument]: function inc takes an argument by reference (ref logic [3:0] x): yosys does not read ref, and yosys-slang drops it, so the variable it is called with would never change on the board. Fix: pass the value in and return it (function automatic logic [3:0] inc(input logic [3:0] x); ... return x + 1;  and  v = inc(v);). https://nosey-dewdrop.github.io/dewfpga/errors/ref-argument/

Why does it happen?

ref arguments are a simulation-time feature that neither open-source reader implements; yosys-slang's silent drop is the worse case, so the scan stops the build with the line.

What is the fix?

function automatic logic [3:0] inc(input logic [3:0] x);
  return x + 1;
endfunction

and v = inc(v); at the call.

Which command prints it?

Which probes in test/sv print this code?

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.