SystemVerilog probes · 103Vivado: supported
a package in its own file (pkg.sv: localparam, typedef, function), imported inside two modules in two files (design.sv, sub.sv), no `include anywhere
Vivado: supported. The open-source chain: all four stages pass.
| stage | today |
|---|---|
| rtl, simulation | pass |
| synth, synthesis | pass |
| netlist, the netlist | pass |
| bit, the bitstream | pass |
What does Vivado do with it?
Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Package declarations', 'Referencing data in packages': Supported; the guide does not say in which order a project's files are compiled
What does the open-source chain do with it?
since #33 the CLI hands pkg.sv first: rtl: 'iverilog -g2012 -o top_sim pkg.sv design.sv sub.sv tb.sv', PASS; bit: yosys' own reader refused the code and yosys-slang read it ('note [read-with-slang]'), 'pnr ok: 2 LUT, 0 FF, no clocked paths, timing not applicable'; netlist: 'EQV PASS: 1048576 output bits compared, all equal', the RTL's registers listed by yosys-slang
Which error pages explain the messages?
- read-with-slang: Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.
What is the probe's code?
From test/sv/103_package_file_two_users.
design.sv
module top(input logic [15:0] sw, output logic [15:0] led);
import cfg_pkg::*;
nib_t hi;
sub u_sub (.a(sw[3:0]), .y(led[3:0]));
assign hi = sw[7:4] & MAGIC;
assign led[7:4] = hi;
assign led[15:8] = '0;
endmodule
pkg.sv
package cfg_pkg; // alone in its file, no `include anywhere: two modules import it
localparam logic [3:0] MAGIC = 4'hA;
typedef logic [3:0] nib_t;
function automatic nib_t twice(input nib_t x);
twice = x << 1;
endfunction
endpackage
sub.sv
module sub(input logic [3:0] a, output logic [3:0] y);
import cfg_pkg::*;
assign y = twice(a) ^ MAGIC;
endmodule
tb.sv
module tb;
reg [15:0] sw = 16'h0000;
wire [15:0] led;
integer i;
top dut(.sw(sw), .led(led));
initial begin
for (i = 0; i < 256; i = i + 1) begin
sw = {8'hC3, i[7:0]}; #1
if (!(led === {8'd0, sw[7:4] & 4'hA, 4'(sw[3:0] << 1) ^ 4'hA})) begin $display("FAIL: package used from two files (sw=%h led=%h)", sw, led); $finish; end
end
$display("PASS"); $finish;
end
endmodule
previous: the same instance connected by name, sub #(.N(8)) u (.sub_in(sub_in), .sub_out(sub_out)), with 4-bit signals
next: two package files where a_pkg.sv imports z_pkg (declared in z_pkg.sv) and the design imports a_pkg::*; alphabetical order reads a_pkg.sv first