SystemVerilog probes · 103bVivado: supported

two package files where a_pkg.sv imports z_pkg (declared in z_pkg.sv) and the design imports a_pkg::*; alphabetical order reads a_pkg.sv first

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Package declarations', 'Referencing data in packages': Supported; the guide does not say in which order a project's files are compiled

What does the open-source chain do with it?

since #33 the CLI orders a package before the file that names it: rtl: 'iverilog -g2012 -o top_sim z_pkg.sv a_pkg.sv design.sv tb.sv', PASS; bit: 'note [read-with-slang]', 'pnr ok: 2 LUT, 0 FF, no clocked paths, timing not applicable'; netlist: the testbench prints PASS, the eqv half 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist' (test/sv/eqv.sh hands iverilog the package files in alphabetical order, a_pkg.sv before z_pkg.sv; the product's order is the fix, not applied to eqv.sh here)

Which error pages explain the messages?

• read-with-slang: Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.

What is the probe's code?

From test/sv/103b_two_packages_order.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  import a_pkg::*;
  assign led[3:0]  = sw[3:0] ^ K;
  assign led[15:4] = '0;
endmodule

a_pkg.sv

package a_pkg;                       // sorts first by name, uses z_pkg: z_pkg.sv has to be read before this file
  import z_pkg::*;
  localparam logic [3:0] K = BASE + 4'h1;
endpackage

z_pkg.sv

package z_pkg;                       // sorts last by name, and a_pkg needs it first
  localparam logic [3:0] BASE = 4'h5;
endpackage

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'hC3, i[7:0]}; #1
      if (!(led === {12'd0, sw[3:0] ^ 4'h6})) begin $display("FAIL: two packages, one importing the other (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: a package in its own file (pkg.sv: localparam, typedef, function), imported inside two modules in two files (design.sv, sub.sv), no `include anywhere
next: a package in its own file (pkg.sv) that design.sv `includes on line 1, 23c's documented fix