SystemVerilog probes · 103cVivado: supported

a package in its own file (pkg.sv) that design.sv `includes on line 1, 23c's documented fix

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Package declarations', 'Referencing data in packages': Supported; Ch.10 'Compilation Units' (p.270)

What does the open-source chain do with it?

the `include brings pkg.sv in and the CLI leaves it to the `include: rtl: 'iverilog -g2012 -o top_sim design.sv tb.sv', PASS; bit: read by yosys' own reader, 'pnr ok: 2 LUT, 0 FF, no clocked paths, timing not applicable'; netlist: the testbench prints PASS, the eqv half 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist' (test/sv/eqv.sh hands iverilog pkg.sv and design.sv both, so the package is declared twice there)

What is the probe's code?

From test/sv/103c_package_file_included.

design.sv

`include "pkg.sv"
module top(input logic [15:0] sw, output logic [15:0] led);
  assign led[3:0]  = cfg_pkg::MAGIC ^ sw[3:0];     // pkg.sv is brought in by the `include above: read once
  assign led[7:4]  = sw[7:4] << cfg_pkg::SHIFT;
  assign led[15:8] = '0;
endmodule

pkg.sv

package cfg_pkg;
  localparam logic [3:0] MAGIC = 4'hA;
  parameter int SHIFT = 1;
endpackage

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'hC3, i[7:0]}; #1
      if (!(led === {8'd0, sw[6:4], 1'b0, sw[3:0] ^ 4'hA})) begin $display("FAIL: package constants (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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