SystemVerilog probes · 102cVivado: supported

the same instance connected by name, sub #(.N(8)) u (.sub_in(sub_in), .sub_out(sub_out)), with 4-bit signals

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Module instantiation syntax: Supported'; a named connection is an assignment, padded or cut to the port's width (IEEE 1800-2017 23.3.2.2)

What does the open-source chain do with it?

a named connection is an assignment, so the readers resize it: rtl: iverilog warns 'design.sv:7: warning: Port 1 (sub_in) of module sub expects 8 bit(s), given 4.', 'Padding 4 high bits of the port.' and prints PASS; bit: yosys' own reader prints 'Warning: Resizing cell port top.u.sub_in from 4 bits to 8 bits.' and 'Warning: Resizing cell port top.u.sub_out from 4 bits to 8 bits.', passed through, 'pnr ok: 4 LUT, 0 FF, no clocked paths, timing not applicable'; netlist equals the RTL ('EQV PASS'); not [implicit-port-width]

Which error pages explain the messages?

• implicit-port-width: A .* or .name port connection whose port and signal widths differ: the simulator pads or cuts and runs, neither synthesis reader builds it; the same line at sim and at bit names the port, the two widths and the fix.

What is the probe's code?

From test/sv/102c_named_conn_width.

design.sv

module sub #(parameter N = 4) (input logic [N-1:0] sub_in, output logic [N-1:0] sub_out);
  assign sub_out = ~sub_in;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] sub_in, sub_out;
  assign sub_in = sw[3:0];
  sub #(.N(8)) u (.sub_in(sub_in), .sub_out(sub_out));
  assign led = {12'b0, sub_out};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0005; #1
    if (!(led === {12'b0, ~sw[3:0]})) begin $display("FAIL: led=%h for sw=%h", led, sw); $finish; end
    sw = 16'h000a; #1
    if (!(led === {12'b0, ~sw[3:0]})) begin $display("FAIL: led=%h for sw=%h", led, sw); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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