SystemVerilog probes · 102bVivado: supported

the same .* connection with the signals declared the port's width (logic [7:0] sub_in, sub_out)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 (p.281-282): 'lower my_inst (.*);'; Ch.10 Table 27 (p.287): 'Module instantiation syntax: Supported'

What does the open-source chain do with it?

read by yosys' own reader (no read-with-slang note), 'pnr ok: 8 LUT, 0 FF, no clocked paths, timing not applicable'; netlist equals the RTL ('EQV PASS')

What is the probe's code?

From test/sv/102b_dotstar_param_equal.

design.sv

module sub #(parameter N = 4) (input logic [N-1:0] sub_in, output logic [N-1:0] sub_out);
  assign sub_out = ~sub_in;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  logic [7:0] sub_in, sub_out;
  assign sub_in = sw[7:0];
  sub #(.N(8)) u (.*);
  assign led = {8'b0, sub_out};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0005; #1
    if (!(led === {8'b0, ~sw[7:0]})) begin $display("FAIL: led=%h for sw=%h", led, sw); $finish; end
    sw = 16'h00a3; #1
    if (!(led === {8'b0, ~sw[7:0]})) begin $display("FAIL: led=%h for sw=%h", led, sw); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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