SystemVerilog probes · 102Vivado: unverified

a .* connection whose port (N bits, N = 8) and signal (4 bits) widths differ

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.10 (p.281-282) lists 'lower my_inst (.*);' and '.name' connections as supported and does not say what Vivado does when the port's width and the signal's differ; slang's own source calls the implicit conversion a restriction of the LRM (IEEE 1800-2017 23.3.2.3)

What does the open-source chain do with it?

since #33 dewfpga sim and dewfpga bit print the same coded line; rtl: iverilog pads and runs ('design.sv:7: warning: Port 1 (sub_in) of module sub expects 8 bit(s), given 4.', 'Padding 4 high bits of the port.'), dewfpga sim refuses with the build's line: "design.sv:7: ERROR [implicit-port-width]: the .* connection of u (module sub) joins the port sub_out, 8 bits wide with N = 8, to the signal sub_out declared 4 bits wide: an implicit connection (.* or .sub_out) takes the port and the signal exactly as declared, with no padding or cutting (IEEE 1800-2017 23.3.2.3), so neither reader builds it, where dewfpga sim (iverilog) widened the signal to the port, so the port's 4 high bits reach nothing (its line: Padding 4 high bits of the port) and ran. Fix: declare sub_out with the port's width (logic [7:0] sub_out;), or connect it by name, .sub_out(sub_out), which pads or cuts to the port's width as the simulation did."; bit: yosys' own reader stops, 'ERROR: Width mismatch between wire (4 bits) and port (8 bits) for implicit port connection `sub_out' of cell top.u', then the same [implicit-port-width] line, and the second reader is not tried. Before #33: PASS from the simulation and two [slang-refused] lines from the build

Which error pages explain the messages?

• implicit-port-width: A .* or .name port connection whose port and signal widths differ: the simulator pads or cuts and runs, neither synthesis reader builds it; the same line at sim and at bit names the port, the two widths and the fix.
• slang-refused: Both readers refused the code; yosys' own line is printed first, then yosys-slang's error with its caret.

What is the probe's code?

From test/sv/102_dotstar_param_width.

design.sv

module sub #(parameter N = 4) (input logic [N-1:0] sub_in, output logic [N-1:0] sub_out);
  assign sub_out = ~sub_in;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] sub_in, sub_out;
  assign sub_in = sw[3:0];
  sub #(.N(8)) u (.*);
  assign led = {12'b0, sub_out};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0005; #1
    if (!(led === {12'b0, ~sw[3:0]})) begin $display("FAIL: led=%h for sw=%h", led, sw); $finish; end
    sw = 16'h000a; #1
    if (!(led === {12'b0, ~sw[3:0]})) begin $display("FAIL: led=%h for sw=%h", led, sw); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: an always_latch whose gate (s < sw) and data (sw < 16'd1791) come from the same inputs, so both change at once (seed 7 of test/fuzz, shrunk)
next: the same .* connection with the signals declared the port's width (logic [7:0] sub_in, sub_out)