errors · bitdewfpga bit, yosys-slang, after yosys' own reader refused the code

blink.v:8: ERROR [slang-refused]: use of undeclared identifier 'logic' (yosys-slang, the second reader; yosys' own reader refused this code too, its line is above). Fix: the caret below marks the construct; the page lists the usual ones and what to write instead.

yosys' reader:
  blink.v:8: ERROR: syntax error, unexpected TOK_ID, expecting ')' or ',' or '='
blink.v:8: ERROR [slang-refused]: use of undeclared identifier 'logic' (yosys-slang, the second reader; yosys' own reader refused this code too, its line is above). Fix: the caret below marks the construct; the page lists the usual ones and what to write instead. https://nosey-dewdrop.github.io/dewfpga/errors/slang-refused/
        input  logic        clk,      // W5: 100 MHz on-board oscillator
               ^~~~~

Why does it happen?

A syntax error (a missing end, a default outside its case), or a construct in a .v file that Verilog-2005 lacks (logic above: see v-is-verilog-2005), or SystemVerilog the readers do not build yet. The usual ones and what to write instead are in the guide's section 8.

What is the fix?

Read yosys-slang's message and the caret; fix the first one, the later ones often follow from it. A .v file holding SystemVerilog:

mv blink.v blink.sv

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• a .* connection whose port (N bits, N = 8) and signal (4 bits) widths differ

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.