errors · bitdewfpga bit, after both readers refused a .v file
note [v-is-verilog-2005]: a .v file is read as Verilog-2005 by both readers, as Vivado reads it (UG901 Ch.10): SystemVerilog (logic, always_ff, always_comb, enum ...) belongs in a .sv file. Fix: if your .v file holds SystemVerilog, rename it to .sv.
yosys' reader:
blink.v:8: ERROR: syntax error, unexpected TOK_ID, expecting ')' or ',' or '='
note [v-is-verilog-2005]: a .v file is read as Verilog-2005 by both readers, as Vivado reads it (UG901 Ch.10): SystemVerilog (logic, always_ff, always_comb, enum ...) belongs in a .sv file. Fix: if your .v file holds SystemVerilog, rename it to .sv. https://nosey-dewdrop.github.io/dewfpga/errors/v-is-verilog-2005/
blink.v:8: ERROR [slang-refused]: use of undeclared identifier 'logic' (yosys-slang, the second reader; yosys' own reader refused this code too, its line is above). Fix: the caret below marks the construct; the page lists the usual ones and what to write instead. https://nosey-dewdrop.github.io/dewfpga/errors/slang-refused/Why does it happen?
Vivado picks the language by the extension (UG901 Ch.10), and so does the CLI, so a .v behaves the same in both: logic is not a Verilog-2005 keyword.
What is the fix?
mv blink.v blink.sv