SystemVerilog probes · 23dVivado: supported

import in the module header: module top import pkg::*; (...)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Using packages in module headers: Supported'

What does the open-source chain do with it?

rtl: 'iverilog -g2012 -o top_sim design.sv tb.sv', PASS; bit: 'note [read-with-slang]: top read with yosys-slang, the second reader', 'pnr ok: 2 LUT, 0 FF'; netlist: the testbench prints PASS on the netlist, then 'EQV PASS: 1048576 output bits compared, all equal' (eqv.sh lists the RTL's registers with yosys-slang, as the build reads it; iverilog runs the RTL side). Measured 8 Oct 2026; before, expect.tsv recorded rtl, synth and bit fail: the CLI's scanner took the ; after the import for the end of the header, saw a module without ports and stopped sim and bit with no design module (only testbenches)

Which error pages explain the messages?

• read-with-slang: Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.

What is the probe's code?

From test/sv/23d_package_header_import.

design.sv

package hdr_pkg;
  localparam logic [3:0] MAGIC = 4'hA;
endpackage
module top import hdr_pkg::*; (input logic [15:0] sw, output logic [15:0] led);   // import in the module header
  assign led = {12'd0, MAGIC ^ sw[3:0]};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 16; i = i + 1) begin
      sw = {12'hF0F, i[3:0]}; #1
      if (!(led === {12'd0, sw[3:0] ^ 4'hA})) begin $display("FAIL: imported constant (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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