SystemVerilog probes · 23eVivado: supported

a package that exports a name it imported: package p2; import p1::K; export p1::K; endpackage, and import p2::* in the module

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Exporting imported names from packages: Supported'

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 2 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/23e_package_export.

design.sv

package p1;
  localparam logic [3:0] K = 4'd9;
endpackage
package p2;
  import p1::K;
  export p1::K;                          // p2 hands on the K it imported from p1
endpackage
module top(input logic [15:0] sw, output logic [15:0] led);
  import p2::*;
  assign led = {sw[15:4], sw[3:0] ^ K};  // K reached through p2
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 256; i++) begin
      sw = {i[7:0], i[7:0]}; #1;
      if (led !== {sw[15:4], sw[3:0] ^ 4'd9}) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 256", bad);
    $finish;
  end
endmodule

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