SystemVerilog probes · 24Vivado: supported

`include of a .svh, `define with arguments, `ifdef/`ifndef/`else, +: part select

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 20 (p.239): '`define', '`ifdef `else `endif', '`undef, `ifndef, `elsif', '`include': Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/24_preproc_include.

design.sv

`include "defs.svh"
`define USE_FEATURE
module top(input logic [15:0] sw, output logic [15:0] led);
  assign led[`WIDTH-1:0] = `MAX(sw[3:0], sw[7:4]);
`ifdef USE_FEATURE
  assign led[4 +: `WIDTH] = 4'hC;
`else
  assign led[7:4] = 4'h3;
`endif
`ifndef NOT_DEFINED
  assign led[15:8] = sw[15:8];
`endif
endmodule

defs.svh

`ifndef DEFS_SVH
`define DEFS_SVH
`define WIDTH 4
`define MAX(a,b) ((a) > (b) ? (a) : (b))
`endif

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'hAB29; #1
    if (!(led === 16'hABC9)) begin $display("FAIL: include/define/ifdef/+: (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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