SystemVerilog probes · 25Vivado: supported

.* and .name implicit port connections

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 (p.281-282): 'lower my_inst (.myout, .clk, .my_in, .my_in2);' and 'lower my_inst (.*);'; UG901 v2023.2 Ch.10 Table 27 (p.287): 'Module instantiation syntax: Supported'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/25_port_conn_dotstar.

design.sv

module adder(input logic [3:0] a, b, output logic [4:0] s);
  assign s = a + b;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] a, b;
  logic [4:0] s, s2;
  assign a = sw[3:0];
  assign b = sw[7:4];
  adder u0 (.*);
  adder u1 (.a, .b(sw[11:8]), .s(s2));
  assign led[4:0] = s;
  assign led[9:5] = s2;
  assign led[15:10] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0321; #1
    if (!(led === 16'h0083)) begin $display("FAIL: .* and .name (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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