SystemVerilog probes · 26Vivado: supported

array of instances: inv u_inv [3:0] (.a(sw[3:0]), .y(led[3:0]));

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 20 (p.239): 'array of instances: Supported'

What does the open-source chain do with it?

builds since #3: the scanner reads inv u_inv [3:0] ( as an instance (it took inv for a second top before), 'pnr ok: 4 LUT, 0 FF', 'top.bit 2.2 MB', netlist PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/26_inst_array.

design.sv

module inv(input logic a, output logic y);
  assign y = ~a;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  inv u_inv [3:0] (.a(sw[3:0]), .y(led[3:0]));
  assign led[15:4] = sw[15:4];
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h1235; #1
    if (!(led === 16'h123A)) begin $display("FAIL: array of instances (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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