SystemVerilog probes · 27Vivado: supported

ROM from initial $readmemh("rom.mem") with async and sync read

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 21 (p.240): '$readmemh: Supported'; Ch.5 'Specifying RAM Initial Contents in an External Data File' (p.155) and 'ROM HDL Coding Techniques' (p.177)

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/27_readmemh_rom.

design.sv

module top(input logic clk, input logic [15:0] sw, output logic [15:0] led);
  logic [7:0] rom [0:15];
  initial $readmemh("rom.mem", rom);
  logic [7:0] rom_q;
  assign led[7:0] = rom[sw[3:0]];              // async read
  always_ff @(posedge clk) rom_q <= rom[sw[7:4]];   // sync read
  assign led[15:8] = rom_q;
endmodule

rom.mem

3C
A5
0F
F0
12
34
56
78
9A
BC
DE
F1
23
45
67
89

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .sw(sw), .led(led));
  initial begin
    sw = 16'h0052; tick;
    if (!(led === 16'h340F)) begin $display("FAIL: rom[2]=0F, rom[5]=34 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h00FA; tick;
    if (!(led === 16'h89DE)) begin $display("FAIL: rom[A]=DE, rom[F]=89 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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