SystemVerilog probes · 28Vivado: supported

RAM: sync write, async read (distributed RAM, -nobram)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.5 'RAM HDL Coding Techniques', Table 3 (p.114): distributed RAM 'Write: Synchronous', 'Read: Asynchronous'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/28_dist_ram.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic [7:0] ram [0:15];
  always_ff @(posedge clk)
    if (btnC) ram[sw[11:8]] <= sw[7:0];
  assign led[7:0] = ram[sw[15:12]];
  assign led[15:8] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  initial begin
    btnC = 1; sw = 16'h035A; tick; sw = 16'h07C3; tick; btnC = 0;
    sw = 16'h3000; #1
    if (!(led[7:0] === 8'h5A)) begin $display("FAIL: ram[3] (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h7000; #1
    if (!(led[7:0] === 8'hC3)) begin $display("FAIL: ram[7] (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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