SystemVerilog probes · 29Vivado: supported

32-deep shift register (SRL) + dynamic tap sr[sw[8:4]]

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.5 'Shift Registers' (p.88) and 'Dynamic Shift Registers' (p.91)

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/29_shift_reg_srl.

design.sv

module top(input logic clk, input logic [15:0] sw, output logic [15:0] led);
  logic [31:0] sr;
  always_ff @(posedge clk) sr <= {sr[30:0], sw[0]};
  assign led[0] = sr[31];            // fixed 32-deep delay line
  assign led[1] = sr[sw[8:4]];       // dynamic tap
  assign led[15:2] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .sw(sw), .led(led));
  initial begin
    sw = 16'h0000; repeat (32) tick;
    sw = 16'h0001; tick; sw = 16'h0050; repeat (5) tick;
    if (!(led[1] === 1'b1)) begin $display("FAIL: tap 5 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    repeat (26) tick;
    if (!(led[0] === 1'b1)) begin $display("FAIL: bit reaches sr[31] (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    tick;
    if (!(led[0] === 1'b0)) begin $display("FAIL: pulse leaves (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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