SystemVerilog probes · 30Vivado: supported

signed 8x8 multiply, >>> arithmetic shift, signed compare, $signed

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.5 'Multipliers' (p.94); UG901 v2023.2 Ch.10 Table 27 (p.286): 'Arithmetic expressions with unsigned and signed types: Supported'; Ch.9 Table 21 (p.240): '$signed: Supported'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/30_mult_signed.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led, output logic [6:0] seg);
  logic signed [7:0] a, b;
  logic signed [15:0] p;
  logic signed [7:0] sh;
  assign a = sw[7:0];
  assign b = sw[15:8];
  assign p = a * b;
  assign sh = a >>> 4;
  assign led = p;
  assign seg[0] = (a < b);
  assign seg[4:1] = sh[3:0];
  assign seg[5] = ($signed(sw[3:0]) < 0);
  assign seg[6] = sh[7];                     // the sign that >>> copies in (>> would shift in 0)
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg;
  integer i, a, b, p, sh;
  top dut(.sw(sw), .led(led), .seg(seg));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      // the reference in plain integers: two's complement by hand, >>> 4 as a floor division by 16
      a = sw[7:0];  if (sw[7])  a = a - 256;
      b = sw[15:8]; if (sw[15]) b = b - 256;
      p = a * b;
      sh = (a >= 0) ? a / 16 : -((15 - a) / 16);
      if (!(led === p[15:0])) begin $display("FAIL: %0d * %0d (sw=%h led=%h)", a, b, sw, led); $finish; end
      if (!(seg === {sh < 0, sw[3] == 1'b1, sh[3:0], a < b})) begin
        $display("FAIL: >>>, $signed or signed < (sw=%h seg=%b, want sh=%0d a<b=%0d)", sw, seg, sh, a < b); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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