SystemVerilog probes · 31Vivado: supported

sync active-high reset, async active-low reset (negedge rst_n), async set to a nonzero constant

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.5 'Flip-Flops, Registers, and Latches' (p.81): 'Asynchronous Set/Reset', 'Synchronous Set/Reset'; FDCE, FDPE, FDSE, FDRE (p.82)

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/31_reset_styles.

design.sv

module top(input logic clk, input logic btnC, input logic btnU, input logic [15:0] sw, output logic [15:0] led);
  logic rst_n;
  logic [3:0] c_sync, c_async, c_set;
  assign rst_n = sw[15];
  always_ff @(posedge clk)                      // sync, active high
    if (btnC) c_sync <= '0; else c_sync <= c_sync + 4'd1;
  always_ff @(posedge clk or negedge rst_n)     // async, active low
    if (!rst_n) c_async <= '0; else c_async <= c_async + 4'd1;
  always_ff @(posedge clk or posedge btnU)      // async set to a nonzero constant
    if (btnU) c_set <= 4'hA; else c_set <= c_set - 4'd1;
  assign led = {4'd0, c_set, c_async, c_sync};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .btnU(btnU), .sw(sw), .led(led));
  initial begin
    sw = 16'h0000; btnU = 1; #1 btnC = 1; tick; btnC = 0; btnU = 0; sw = 16'h8000; #1
    if (!(led === 16'h0A00)) begin $display("FAIL: after resets (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    tick; tick; tick;
    if (!(led === 16'h0733)) begin $display("FAIL: 3 clocks (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0000; #1
    if (!(led === 16'h0703)) begin $display("FAIL: async clear without clock (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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