SystemVerilog probes · 99Vivado: unverified

a parameter of type string: parameter string INIT_FILE = "digits.mem" (a ROM that takes its $readmemh file as a parameter)

Vivado: unverified. The open-source chain: all four stages pass.

What does Vivado do with it?

Unverified. UG901 v2023.2 does not say what Vivado does with a parameter of type string: Ch.10 Table 27 (p.285) has no row for the string type, Ch.9 Table 20 (p.238) lists the constant type String as Unsupported while the example on p.247 declares an untyped string parameter (parameter component = "TMS380C16"), and p.232 says 'Null string parameters are not supported'. No Vivado log in the corpus uses one

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code: 'note [read-with-slang]: top read with yosys-slang, the second reader'; rtl: PASS; bit: 'pnr ok: 7 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

Which error pages explain the messages?

• read-with-slang: Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.

What is the probe's code?

From test/sv/99_string_parameter.

design.sv

// a ROM module that takes its $readmemh file as a string parameter
module rom #(parameter string INIT_FILE = "digits.mem") (input logic [3:0] a, output logic [7:0] q);
  logic [7:0] m [0:15];
  initial $readmemh(INIT_FILE, m);
  assign q = m[a];
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  rom u(.a(sw[3:0]), .q(led[7:0]));
  assign led[15:8] = '0;
endmodule

digits.mem

01
0c
17
22
2d
38
43
4e
59
64
6f
7a
85
90
9b
a6

tb.sv

module tb;
  logic [15:0] sw = 0; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 16; i++) begin
      sw = {12'hfff, i[3:0]};                           // digits.mem holds i * 11 + 1 at address i
      #1 if (led !== 16'(i * 11 + 1)) begin bad++; if (bad < 4) $display("FAIL: address %0d led=%h", i, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 16", bad);
    $finish;
  end
endmodule

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