SystemVerilog probes · 98Vivado: unverified

a student's module named like a Xilinx primitive: module INV (GND, VCC and MUXF7 too)

Vivado: unverified. The open-source chain: all four stages pass.

What does Vivado do with it?

Unverified. UG901 v2023.2 does not say what Vivado does with a user module named like a primitive; Ch.9 (p.232) instantiates AMD primitives from unisim_comp.v. No Vivado log in the corpus: none of its modules has such a name

What does the open-source chain do with it?

rtl: PASS; bit: 'pnr ok: 1 LUT, 0 FF, no clocked paths, timing not applicable'; netlist testbench: PASS. The current recipe reads this case with Yosys' native reader; before the 8 October candidate the build used the yosys-slang fallback and printed its reader note. Vivado behavior remains unverified.

What is the probe's code?

From test/sv/98_module_named_primitive.

design.sv

// a student's own inverter, named INV: the same name as a Xilinx primitive in yosys' cell library
module INV(input logic a, output logic y);
  assign y = ~a;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  INV u0(.a(sw[0]), .y(led[0]));
  assign led[15:1] = sw[15:1];
endmodule

tb.sv

module tb;
  logic [15:0] sw = 0; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 64; i++) begin
      sw = (i < 32) ? 16'(i) : $random;
      #1 if (led !== {sw[15:1], ~sw[0]}) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 64", bad);
    $finish;
  end
endmodule

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