SystemVerilog probes · 97Vivado: supported

UG901's RAM_STYLE attribute: (* ram_style = "block" *) on a 256-byte memory, written with btnC and read one clock later

Vivado: supported. The open-source chain: it builds a bitstream, and the netlist check fails.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.3 RAM_STYLE (p.64): 'block: Instructs the tool to infer RAMB-type components.'

What does the open-source chain do with it?

yosys honors the attribute despite -nobram, so the memory becomes one RAMB18E1 (yosys' own log says forced mapping to block RAM; the CLI does not show it): 'Warning: No clocks found in design', 'pnr ok: 0 LUT, 0 FF, no clocked paths, timing not applicable', so the block RAM is not timed. netlist: no RAMB18E1 model (yosys' cells_sim.v gives it timing only), so the netlist reads z and fails the testbench; the bitstream is built but not checked on a board. README and the guide said every memory becomes LUTs; they name this exception now

What is the probe's code?

From test/sv/97_ram_style_block.

design.sv

// UG901's RAM_STYLE attribute asks for a block RAM: 256 bytes, written with btnC, read one clock later
module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  (* ram_style = "block" *) logic [7:0] mem [0:255];
  always_ff @(posedge clk) begin
    if (btnC) mem[sw[15:8]] <= sw[7:0];
    led <= {8'b0, mem[sw[15:8]]};
  end
endmodule

tb.sv

module tb;
  logic clk = 0, btnC = 0; logic [15:0] sw = 0; logic [15:0] led;
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  always #5 clk = ~clk;
  integer i, bad = 0;
  initial begin
    btnC = 1;                                   // write address a with a * 7 + 3 (low byte)
    for (i = 0; i < 256; i++) begin sw = {i[7:0], 8'(i * 7 + 3)}; @(negedge clk); end
    btnC = 0;                                   // read every address back, in another order
    for (i = 0; i < 256; i++) begin
      sw = {8'(i * 37), 8'hff}; @(negedge clk);
      if (led !== {8'h00, 8'(i * 37 * 7 + 3)}) begin bad++; if (bad < 4) $display("FAIL: address %0d led=%h", 8'(i * 37), led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 256", bad);
    $finish;
  end
endmodule

previous: ports numbered from 1: input logic [4:1] sw, output logic [4:1] led, with the lab's own XDC, whose lines for sw[1] to sw[4] and led[1] to led[4] are uncommented
next: a student's module named like a Xilinx primitive: module INV (GND, VCC and MUXF7 too)