SystemVerilog probes · 96bVivado: supported

ports numbered from 1: input logic [4:1] sw, output logic [4:1] led, with the lab's own XDC, whose lines for sw[1] to sw[4] and led[1] to led[4] are uncommented

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Vector declarations: Supported'. [4:1] has bits 1 to 4 (IEEE 1800-2017 7.4), the pins the XDC names

What does the open-source chain do with it?

XDC validation preserves the declared vector indices; RTL and netlist equivalence pass, pin validation and place-and-route pass, and the resulting FASM produces a bitstream. Source ports and pin assignments are unchanged.

What is the probe's code?

From test/sv/96b_port_offset_range, next to the lab's own Basys3_Master.xdc.

design.sv

// ports numbered from 1, as some lab handouts number the switches: sw[1] to sw[4]
module top(input logic [4:1] sw, output logic [4:1] led);
  assign led = ~sw;
endmodule

tb.sv

module tb;
  logic [4:1] sw = 0; logic [4:1] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 16; i++) begin sw = i[3:0]; #1 if (led !== ~sw) bad++; end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 16", bad);
    $finish;
  end
endmodule

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