SystemVerilog probes · 96Vivado: supported

a port declared [N-1:0] with N = 1: a vector of one bit, numbered 0

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Vector declarations: Supported'. [N-1:0] with N = 1 is a vector of one bit numbered 0 (IEEE 1800-2017 7.4), so its pins in the XDC are sw[0] and led[0]

What does the open-source chain do with it?

XDC validation preserves the declared vector indices; RTL and netlist equivalence pass, pin validation and place-and-route pass, and the resulting FASM produces a bitstream. Source ports and pin assignments are unchanged.

What is the probe's code?

From test/sv/96_port_one_bit_vector.

design.sv

// a module written for any width, used at width 1: its ports are [0:0], one bit numbered 0 (sw[0], led[0])
module top #(parameter int N = 1) (input logic [N-1:0] sw, output logic [N-1:0] led);
  assign led = ~sw;
endmodule

tb.sv

module tb;
  logic [0:0] sw = 0; logic [0:0] led;
  top dut(.sw(sw), .led(led));
  integer bad = 0;
  initial begin
    sw = 1'b0; #1 if (led !== 1'b1) bad++;
    sw = 1'b1; #1 if (led !== 1'b0) bad++;
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 2", bad);
    $finish;
  end
endmodule

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