SystemVerilog probes · 95Vivado: unverified

a submodule declared with its ports and no body (a lab part not written yet), its output used by top

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. No Vivado log in the corpus: its 2 modules with ports and no body sit in lab folders with no Vivado run, and UG901 v2023.2 does not say what Vivado does with such a module. Vivado logs in the corpus (2015.2, 2021.2) warn on a net with no driver, [Synth 8-3848], and go on

What does the open-source chain do with it?

yosys reads the empty module as a blackbox, so the netlist keeps a cell of type blinker: nextpnr stops with 'no Bels remaining of type 'blinker'', which since #5 the CLI reads as 'design.sv:2: ERROR [empty-module]: the module blinker (design.sv:2), instantiated as u_blink, has no body (no assign, no always), so yosys kept it as a black box, and nextpnr has no cell of that type to place. Not a size problem. Fix: write the body of blinker, or comment the instance u_blink out until it is written.' (before #5: the design does not fit the XC7A35T, naming neither the module nor the instance); the netlist, written back, has no module for that cell (Unknown module type: blinker). dewfpga sim runs, led[0] z. With b unused it builds, 0 LUT (measured apart)

Which error pages explain the messages?

• empty-module: An instance of a module with ports and no body; yosys keeps it as a black box, nextpnr has no cell of that type.

What is the probe's code?

From test/sv/95_empty_submodule.

design.sv

// a lab mid-way: part 2's module is declared and instantiated, its body not written yet
module blinker(input logic clk, output logic led);
  // part 2 of the lab: not written yet
endmodule
module top(input logic clk, input logic [15:0] sw, output logic [15:0] led);
  logic b;
  blinker u_blink(.clk(clk), .led(b));
  assign led = {sw[15:1], b};
endmodule

tb.sv

module tb;
  // part 1, the switches on led[15:1], is what is written so far; led[0] waits for part 2
  logic clk = 0; logic [15:0] sw = 0; logic [15:0] led;
  top dut(.clk(clk), .sw(sw), .led(led));
  always #5 clk = ~clk;
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 300; i++) begin
      sw = (i < 16) ? 16'(1 << i) : $random;
      @(negedge clk); if (led[15:1] !== sw[15:1]) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 300", bad);
    $finish;
  end
endmodule

previous: a variable raised to a constant power: assign led = sw[7:0] ** 2;
next: a port declared [N-1:0] with N = 1: a vector of one bit, numbered 0