SystemVerilog probes · 95bVivado: unverified

the same module defined in two files of the folder (design.sv and a backup design_old.sv), an older body in the backup

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. No Vivado log of this case in the corpus; UG901 does not say which definition Vivado takes when two files define one module

What does the open-source chain do with it?

the scanner stops sim and bit before make and names both definitions: 'design.sv:1: ERROR [module-defined-twice]: module top is defined twice: design.sv:1 and design_old.sv:2; the last one read would win silently. Fix: keep one, or move the backup out of this folder.'; before, the last file read won silently and the backup's body could be built

Which error pages explain the messages?

• module-defined-twice: Two files in the folder declare the same module; the tools would take the last one read, so a backup could be built instead of the design.

What is the probe's code?

From test/sv/95b_module_in_two_files.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);   // the lab as handed in
  assign led = sw;
endmodule

design_old.sv

// a backup the student kept next to the real file (lab4_old.sv): the same module name, an older body
module top(input logic [15:0] sw, output logic [15:0] led);
  assign led = ~sw;
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = i * 16'h0101; #1
      if (led !== sw) begin $display("FAIL: led=%h for sw=%h: the backup module was built", led, sw); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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