SystemVerilog probes · 100Vivado: unverified

a unique casez whose items overlap: 4'b10?? and 4'b??11 both match 4'b1011 (the simulation takes the first item, the hardware ORs both)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.10 (p.279) says Vivado synthesis treats unique case as parallel_case and full_case, and does not say what Vivado does when two unique items both match; no Vivado log. The netlist the build makes ORs the items (seed 6 of test/fuzz: rtl 0000000000000001, net 0000000000000011).

What does the open-source chain do with it?

the scanner sees two items of a unique casez that match one value and stops sim and bit before make: 'design.sv:5: ERROR [unique-case-overlap]: the items 4'b10?? (design.sv:4) and 4'b??11 (design.sv:5) of this unique casez both match 4'b1011, and unique promises that only one item can match: the simulation takes the first item (iverilog ignores unique), and the hardware, built as parallel logic the way Vivado builds a unique case (UG901 Ch.10, parallel_case), ORs the two items' then 'so the board would not do what the simulation showed. Fix: make the items disjoint (4'b10?? and 4'b0?11), write priority casez when the first match should win, or drop unique.'; no top.json, no top.bit. A unique case whose items are disjoint still passes (18_unique_priority)

Which error pages explain the messages?

• unique-case-overlap: Two items of a unique casez (or casex) can match the same value; the simulator takes the first, the hardware ORs both, so the board would not do what the simulation showed.

What is the probe's code?

From test/sv/100_unique_casez_overlap.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  always_comb
    unique casez (sw[3:0])
      4'b10??: led = 16'd1;
      4'b??11: led = 16'd2;
      default: led = 16'd0;
    endcase
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  top dut(.sw(sw), .led(led));
  // first-match semantics, as iverilog simulates it (it ignores unique): sw = 000B matches both items and
  // the simulation takes the first (led = 1); the netlist ORs both items (led = 3), so the board would differ
  initial begin
    sw = 16'h000B; #1 if (led !== 16'd1) begin $display("FAIL: sw=%h led=%h, expected 1", sw, led); $finish; end
    sw = 16'h0008; #1 if (led !== 16'd1) begin $display("FAIL: sw=%h led=%h, expected 1", sw, led); $finish; end
    sw = 16'h0003; #1 if (led !== 16'd2) begin $display("FAIL: sw=%h led=%h, expected 2", sw, led); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: the same module defined in two files of the folder (design.sv and a backup design_old.sv), an older body in the backup
next: always_latch if (sw[1]) q = sw[0]; (a latch on purpose, sw[1] its gate), read by yosys' own reader