SystemVerilog probes · 101Vivado: supported

always_latch if (sw[1]) q = sw[0]; (a latch on purpose, sw[1] its gate), read by yosys' own reader

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.5 Latches (p.84): the LDCE Vivado builds for a latch (the 01_latch_comb source)

What does the open-source chain do with it?

builds, and bit.log holds one warning at the always_latch line: 'design.sv:3: warning [latch-hazard]: always_latch builds a latch for q (an LDCE cell, as Vivado builds it, UG901 Ch.5 Latches), and a latch has no clock: when its gate (sw[1]) closes in the same instant its data changes, the board keeps the old value or takes the new one depending on which wire is faster, where the simulation always keeps the old one; dewfpga sim cannot show that race. Fix: if a register was meant, write always_ff @(posedge clk) with the gate as its enable: if (sw[1]) q <= ...; keep always_latch only when the gate is held steady while the data changes.'; bit: 'pnr ok: 0 LUT, 1 FF, no clocked paths, timing not applicable'

Which error pages explain the messages?

• latch-hazard: An always_latch whose gate and data come from the same inputs: when both change at once the board races, where the simulation keeps the old value; the build goes on with the warning.

What is the probe's code?

From test/sv/101_always_latch.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic q;
  always_latch if (sw[1]) q = sw[0];   // a latch on purpose: sw[1] is its gate
  assign led = {15'b0, q};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0003; #1
    if (!(led[0] === 1'b1)) begin $display("FAIL: open latch must pass sw[0]=1 (led=%h)", led); $finish; end
    sw = 16'h0001; #1 sw = 16'h0000; #1
    if (!(led[0] === 1'b1)) begin $display("FAIL: closed latch must hold 1 (led=%h)", led); $finish; end
    sw = 16'h0002; #1
    if (!(led[0] === 1'b0)) begin $display("FAIL: open latch must pass sw[0]=0 (led=%h)", led); $finish; end
    sw = 16'h0000; #1 sw = 16'h0001; #1
    if (!(led[0] === 1'b0)) begin $display("FAIL: closed latch must hold 0 (led=%h)", led); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: a unique casez whose items overlap: 4'b10?? and 4'b??11 both match 4'b1011 (the simulation takes the first item, the hardware ORs both)
next: the same always_latch next to a foreach loop (43_foreach_loop), so the design is read with yosys-slang