errors · bitdewfpga sim / bit, the source scan before the tools run

design.sv:1: ERROR [module-defined-twice]: module top is defined twice: design.sv:1 and design_old.sv:2; the last one read would win silently. Fix: keep one, or move the backup out of this folder.

design.sv:1: ERROR [module-defined-twice]: module top is defined twice: design.sv:1 and design_old.sv:2; the last one read would win silently. Fix: keep one, or move the backup out of this folder. https://nosey-dewdrop.github.io/dewfpga/errors/module-defined-twice/

Why does it happen?

A backup (design_old.sv, design copy.sv) kept next to the design. Vivado projects list their sources, so a stray file does nothing there; the CLI reads every file of the folder.

What is the fix?

mkdir -p old && mv design_old.sv old/

Which command prints it?

• dewfpga sim
• dewfpga bit

Which probes in test/sv print this code?

• the same module defined in two files of the folder (design.sv and a backup design_old.sv), an older body in the backup

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.