errors · bitdewfpga bit, yosys

design.sv:3 and design.sv:4: ERROR [two-always-drivers]: cnt is written from two always blocks (design.sv:3 and design.sv:4): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive cnt from one always block (merge the two, or give each block its own signal).

yosys' own warnings name only cells; the CLI reads the cells' source lines from the elaborated design and names both blocks.

Warning: multiple conflicting drivers for top.\cnt [3]:
    port Q[3] of cell $driver$cnt_1 ($dff)
    port Q[3] of cell $driver$cnt ($dff)
design.sv:3 and design.sv:4: ERROR [two-always-drivers]: cnt is written from two always blocks (design.sv:3 and design.sv:4): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive cnt from one always block (merge the two, or give each block its own signal). https://nosey-dewdrop.github.io/dewfpga/errors/two-always-drivers/

Why does it happen?

Each always block becomes its own set of flip-flops; two blocks writing one signal are two drivers on one wire. The simulator picks the last write; the chip cannot.

What is the fix?

always_ff @(posedge clk)
  if (btnC) cnt <= '0;
  else cnt <= cnt + 1;

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• one reg written from two always blocks on different edges (posedge btnU / posedge btnC)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.