SystemVerilog probes · 05Vivado: unverified

one reg written from two always blocks on different edges (posedge btnU / posedge btnC)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. Not in UG901. Weak source only: AMD community forum posts quote 'Synth 8-6859 multi-driven net' (critical warning) and then DRC MDRV-1 (an error, no bitstream)

What does the open-source chain do with it?

dewfpga bit stops, no bitstream: yosys' 'multiple conflicting drivers for top.\cnt' warning names only cells, so the Makefile reads the cells' src attributes from top.il (written after proc) and prints 'design.sv:3 and design.sv:4: ERROR [two-always-drivers]: cnt is written from two always blocks (design.sv:3 and design.sv:4): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive cnt from one always block (merge the two, or give each block its own signal).'

Which error pages explain the messages?

• two-always-drivers: The same register is assigned in two always blocks; yosys resolves the conflict silently, Vivado refuses it.

What is the probe's code?

From test/sv/05_two_block_driver.

design.sv

module top(input logic btnU, input logic btnC, output logic [15:0] led);
  logic [3:0] cnt = 4'd0;
  always @(posedge btnU) cnt <= cnt + 4'd1;   // written on one edge
  always @(posedge btnC) cnt <= 4'd0;         // and on another
  assign led = {12'd0, cnt};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.btnU(btnU), .btnC(btnC), .led(led));
  initial begin
    #1 btnU = 1; #5 btnU = 0; #5 btnU = 1; #5 btnU = 0; #5
    if (!(led[3:0] === 4'd2)) begin $display("FAIL: two presses (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    btnC = 1; #5 btnC = 0; #5
    if (!(led[3:0] === 4'd0)) begin $display("FAIL: clear (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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