SystemVerilog probes · 06Vivado: not supported

a case item's begin (S2: begin) never closed before default: (invalid code; a typo seen in a CS223 lab)

Vivado: not supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Not supported. Invalid code: IEEE 1800-2017 A.6.7, case_item ::= case_item_expression {, case_item_expression} : statement_or_null, so S2's begin needs its end before the next item. No Vivado log of this text; iverilog 13 and yosys 0.69 both stop at line 17

What does the open-source chain do with it?

syntax error at design.sv:17 in every tool (expected)

What is the probe's code?

From test/sv/06_missing_end_default.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  typedef enum logic [1:0] {S0, S1, S2} st_t;
  st_t state, nextstate;
  logic [3:0] cnt, nextCnt;
  always_ff @(posedge clk)
    if (btnC) begin state <= S0; cnt <= 0; end
    else begin state <= nextstate; cnt <= nextCnt; end
  always_comb
    case (state)
      S0: begin nextstate = sw[0] ? S1 : S0; nextCnt = cnt; end
      S1: begin nextstate = S2; nextCnt = 0; end
      S2: begin                   // this begin is never closed
        nextstate = S2; nextCnt = cnt;
        if (cnt <= 4'd5) begin
          nextCnt = cnt + 1;
        end
      default: nextstate = S0;    // so the parser meets 'default' inside S2's block
    endcase
  assign led = {10'd0, state, cnt};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  initial begin
    btnC = 1; tick; btnC = 0; #1
    if (!(led[5:4] === 2'd0)) begin $display("FAIL: reset to S0 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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