SystemVerilog probes · 07Vivado: supported

packed array of enums: statetype [1:0] state, nextstate;

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2020.1 synthesis log of a public CS223 lab repo: the module with this declaration: 'INFO: [Synth 8-6155] done synthesizing module '<that module>' (3#1)', 'Synthesis finished with 0 errors'. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Packed arrays', 'Enumerations': Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/07_enum_packed_array.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  typedef enum logic [1:0] {S0, S1, S2} statetype;
  statetype [1:0] state, nextstate;     // packed array of enums (seen in a CS223 lab that Vivado built)
  always_ff @(posedge clk)
    if (btnC) state <= S0; else state <= nextstate;
  always_comb
    case (state)
      S0: nextstate = sw[0] ? S1 : S0;
      S1: nextstate = S2;
      S2: nextstate = S0;
      default: nextstate = S0;
    endcase
  assign led = {12'd0, state};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  initial begin
    btnC = 1; tick; btnC = 0; #1
    if (!(led[3:0] === 4'd0)) begin $display("FAIL: reset S0 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0001; tick;
    if (!(led[3:0] === 4'd1)) begin $display("FAIL: S1 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    tick;
    if (!(led[3:0] === 4'd2)) begin $display("FAIL: S2 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    tick;
    if (!(led[3:0] === 4'd0)) begin $display("FAIL: back to S0 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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