SystemVerilog probes · 08Vivado: supported

ANSI port inheriting its direction: output [6:0] seg, logic dp, (the course's seven-segment file)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2020.1 synthesis log of a public CS223 lab repo: the course's seven-segment module with this port line: 'INFO: [Synth 8-6155] done synthesizing module '<the seven-segment module>' (4#1)', 'Synthesis finished with 0 errors'

What does the open-source chain do with it?

the CLI writes the direction into the port line in place and prints 'design.sv:2: note [port-neither-input-nor-output]: wrote the port direction in:'; yosys then builds it

Which error pages explain the messages?

• port-neither-input-nor-output: The course's seven-segment module has a broken port line. Vivado accepts it, Yosys does not.

What is the probe's code?

From test/sv/08_port_dir_inherit.

design.sv

module top(input logic clk, input logic [15:0] sw,
           output [6:0] seg, logic dp,     // course SevenSegmentDisplay.sv port line: dp inherits 'output'
           output [3:0] an);
  assign seg = ~sw[6:0];
  assign dp = sw[7];
  assign an = ~sw[11:8];
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .sw(sw), .seg(seg), .dp(dp), .an(an));
  initial begin
    sw = 16'h03A5; #1
    if (!(seg === 7'b1011010 && dp === 1'b1 && an === 4'b1100)) begin $display("FAIL: port values (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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