errors · 7dewfpga bit, the source scan before the tools run (Yosys alone prints the raw form below)

design.sv:3: note [port-neither-input-nor-output]: wrote the port direction in: output logic dp, (in the copy the tools read, your file stays as you wrote it; the standard and Yosys need it; Vivado accepts both)

The CLI supplies the inherited direction in a temporary compiler copy and prints a note; the build goes on and your saved source stays unchanged:

design.sv:3: note [port-neither-input-nor-output]: wrote the port direction in:  output logic dp,   (in the copy the tools read, your file stays as you wrote it; the standard and Yosys need it; Vivado accepts both) https://nosey-dewdrop.github.io/dewfpga/errors/port-neither-input-nor-output/

Yosys alone, without the CLI, stops with the lines below.

The first lab that uses the seven-segment display stops in synthesis with this line. Simulation was fine.

Why does it happen?

The SevSeg_4digit.sv module that the course hands out declares its ports like this.

output [6:0]seg, logic dp,     // dp takes output from seg, per the standard

The standard reads it as output logic dp: a port without a direction takes the one before it. Vivado accepts the line, and so does Icarus Verilog, which is why make sim passes. Yosys does not implement that inheritance and stops.

What is the fix?

output [6:0] seg,
output logic dp,

After the change the module synthesizes to 46 cells and the rest of the lab goes through unchanged.

dewfpga bit makes this change in a temporary compiler copy and prints a note, unless a comment sits between seg, and logic dp, or a comment in the port list holds a ;; then move that comment out. The course's ready modules in netlist form are the other course files that break (section 7.1). This one is also the clearest example of a bigger point: two tools read your code, Icarus for simulation and Yosys for synthesis, and they do not agree on everything. Code that passes make sim can still fail in make bit. Section 7 and section 8 of the guide.

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• ANSI port inheriting its direction: output [6:0] seg, logic dp, (the course's seven-segment file)
• the course's port line (output [6:0] seg, logic dp) with comments in the port list: one after seg, one with a ';' in it
• the course's port line shape with a range only, written in an always block: output logic [6:0] seg, [3:0] an; with an set in an always_comb

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.