SystemVerilog probes · 08bVivado: supported

the course's port line (output [6:0] seg, logic dp) with comments in the port list: one after seg, one with a ';' in it

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. As 08: the course's seven-segment port line builds in Vivado (Vivado 2020.1 synthesis log of a public CS223 lab repo, 'Synthesis finished with 0 errors'); a comment is white space to any Verilog reader (IEEE 1800-2017 5.4)

What does the open-source chain do with it?

'design.sv:3: note [port-neither-input-nor-output]: wrote the port direction in: output logic dp,' (since #5 with the code)

Which error pages explain the messages?

• port-neither-input-nor-output: The course's seven-segment module has a broken port line. Vivado accepts it, Yosys does not.

What is the probe's code?

From test/sv/08b_port_dir_comment.

design.sv

module top(input logic [15:0] sw,   // switches; sw[7] is the dot
           output [6:0] seg,         // cathodes, active low
           logic dp,
           output [3:0] an);
  assign seg = ~sw[6:0];
  assign dp = sw[7];
  assign an = ~sw[11:8];
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i;
  top dut(.sw(sw), .seg(seg), .dp(dp), .an(an));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (!(seg === ~sw[6:0] && dp === sw[7] && an === ~sw[11:8])) begin $display("FAIL: seg, dp, an (sw=%h seg=%b dp=%b an=%b)", sw, seg, dp, an); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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