SystemVerilog probes · 08cVivado: supported

the course's port line shape with a range only, written in an always block: output logic [6:0] seg, [3:0] an; with an set in an always_comb

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2021.2 logs of a public CS223 lab repo: a port list whose last output has only a range (output logic [2:0] <one>, [2:0] <other>), the second written in an always_comb: synthesis 'Synthesis finished with 0 errors, 0 critical warnings and 13 warnings.', implementation 'write_bitstream completed successfully', and its xsim elaborate.log 'Completed static elaboration'. A strict reader (IEEE 1800-2017 23.2.2.3; slang) calls that port a net, which an always block may not write: Vivado is lenient here

What does the open-source chain do with it?

'design.sv:2: note [port-neither-input-nor-output]: wrote the port direction in: output logic [6:0] seg, output logic [3:0] an); // an has only a range: it inherits output from seg (a strict reader makes it a net, not logic)'

Which error pages explain the messages?

• port-neither-input-nor-output: The course's seven-segment module has a broken port line. Vivado accepts it, Yosys does not.

What is the probe's code?

From test/sv/08c_port_dir_inherit_proc.

design.sv

module top(input logic [15:0] sw,
           output logic [6:0] seg, [3:0] an);   // an has only a range: it inherits output from seg (a strict reader makes it a net, not logic)
  assign seg = ~sw[6:0];
  always_comb                                    // an written in an always block
    case (sw[9:8])
      2'd0:    an = 4'b1110;
      2'd1:    an = 4'b1101;
      2'd2:    an = 4'b1011;
      default: an = 4'b0111;
    endcase
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [6:0] seg; logic [3:0] an;
  top dut(.sw(sw), .seg(seg), .an(an));
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 1024; i++) begin
      sw = i; #1;
      if (an !== ~(4'b0001 << sw[9:8]) || seg !== ~sw[6:0]) begin bad++; if (bad < 4) $display("FAIL: sw=%h an=%b seg=%b", sw, an, seg); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 1024", bad);
    $finish;
  end
endmodule

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