SystemVerilog probes · 09Vivado: supported

always_ff / always_comb / always_latch

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.286): 'Combinational logic always_comb procedure', 'Latched logic always_latch procedure', 'Sequential logic always_ff procedure': Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/09_always_procs.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] cnt, dec;
  logic lat;
  always_ff @(posedge clk)
    if (btnC) cnt <= '0; else cnt <= cnt + 4'd1;
  always_comb begin
    dec = '0;
    dec[sw[1:0]] = 1'b1;
  end
  always_latch
    if (sw[2]) lat <= sw[3];
  assign led = {7'd0, lat, dec, cnt};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  initial begin
    btnC = 1; tick; btnC = 0; tick; tick; tick;
    if (!(led[3:0] === 4'd3)) begin $display("FAIL: always_ff counter (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h000E; #1
    if (!(led[7:4] === 4'b0100 && led[8] === 1'b1)) begin $display("FAIL: always_comb decoder / always_latch open (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h000A; #1 sw = 16'h0002; #1
    if (!(led[8] === 1'b1)) begin $display("FAIL: always_latch hold (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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