SystemVerilog probes · 10Vivado: supported

typedef enum FSM with an explicit base type and with the default (int), plus a light_t'(l+1) cast

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Enumerations', 'Enumerated type ranges', 'Cast operator': Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/10_enum_fsm.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  typedef enum logic [1:0] {IDLE = 2'b00, RUN = 2'b01, DONE = 2'b11} state_t;   // explicit base type
  typedef enum {RED, GREEN, YELLOW} light_t;                                     // default base type (int)
  state_t s, ns;
  light_t l;
  always_ff @(posedge clk)
    if (btnC) begin s <= IDLE; l <= RED; end
    else begin s <= ns; l <= (l == YELLOW) ? RED : light_t'(l + 1); end
  always_comb begin
    ns = s;
    case (s)
      IDLE: if (sw[0]) ns = RUN;
      RUN:  ns = DONE;
      DONE: if (!sw[0]) ns = IDLE;
      default: ns = IDLE;
    endcase
  end
  assign led = {10'd0, l[1:0], 2'd0, s};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  // the reference in plain numbers: IDLE=0, RUN=1, DONE=3; RED=0, GREEN=1, YELLOW=2
  integer s, l, i;
  reg [39:0] pattern = 40'b1100_1110_0111_0001_1011_0000_1111_0101_0011_1001;
  initial begin
    btnC = 1; tick; btnC = 0; #1 s = 0; l = 0;
    if (!(led === 16'h0000)) begin $display("FAIL: reset (led=%h)", led); $finish; end
    for (i = 0; i < 40; i = i + 1) begin
      sw[0] = pattern[i]; tick; #1
      case (s)
        0: s = sw[0] ? 1 : 0;
        1: s = 3;
        3: s = sw[0] ? 3 : 0;
      endcase
      l = (l == 2) ? 0 : l + 1;
      if (!(led === {10'd0, l[1:0], 2'd0, s[1:0]})) begin $display("FAIL: step %0d sw[0]=%b: led=%h, want state %0d light %0d", i, sw[0], led, s, l); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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