SystemVerilog probes · 11Vivado: supported

enum methods s.first() / s.next() / s.last()

Vivado: supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Enumerated type methods: Supported'

What does the open-source chain do with it?

yosys: "Can't resolve function name `\s.first'"; since #5 the CLI names the line and the fix: 'design.sv:5: ERROR [enum-method-next-prev]: s.next() is an enum method that steps through the values (next/prev): yosys does not build enum methods, and yosys-slang builds first()/last() only; Vivado builds next/prev (UG901 Ch.10 Table 27). Fix: write the step out as a case on s, in the order the enum lists its values (with IDLE, RUN, DONE: case (s) IDLE: s <= RUN; RUN: s <= DONE; DONE: s <= IDLE; endcase).'

Which error pages explain the messages?

• enum-method-next-prev: The enum methods next() and prev(); neither reader builds them, Vivado does.

What is the probe's code?

From test/sv/11_enum_methods.

design.sv

module top(input logic clk, input logic btnC, output logic [15:0] led);
  typedef enum logic [1:0] {IDLE = 2'd0, RUN = 2'd1, DONE = 2'd3} state_t;
  state_t s;
  always_ff @(posedge clk)
    if (btnC) s <= s.first(); else s <= s.next();
  assign led = {13'd0, (s == s.last()), s};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .led(led));
  initial begin
    btnC = 1; tick; btnC = 0; #1
    if (!(led[2:0] === 3'b000)) begin $display("FAIL: first() (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    tick;
    if (!(led[2:0] === 3'b001)) begin $display("FAIL: next() -> RUN (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    tick;
    if (!(led[2:0] === 3'b111)) begin $display("FAIL: next() -> DONE, last() (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    tick;
    if (!(led[2:0] === 3'b000)) begin $display("FAIL: next() wraps to IDLE (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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