SystemVerilog probes · 12Vivado: supported

typedef struct packed, nested, member read and write

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Structures', 'Packed/Unpacked structures', 'Assigning to structures': Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/12_struct_packed.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  typedef struct packed { logic [3:0] hi; logic [3:0] lo; } byte_t;
  typedef struct packed { logic valid; byte_t data; } pkt_t;
  byte_t b;
  pkt_t p;
  assign b = sw[7:0];
  always_comb begin
    p.valid   = sw[8];
    p.data.hi = b.lo;
    p.data.lo = b.hi;
  end
  assign led[8:0] = p;
  assign led[15:9] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h01A5; #1
    if (!(led === 16'h015A)) begin $display("FAIL: {valid, swapped nibbles} (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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