SystemVerilog probes · 12bVivado: supported

named assignment pattern '{hi: x, lo: y} and '{default: 0}

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.286): 'Structure assignment patterns', 'Array assignment patterns': Supported

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:5: syntax error', and dewfpga sim goes on with 'design.sv:5: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:5: syntax error'; bit: 'pnr ok: 0 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/12b_struct_assign_pattern.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  typedef struct packed { logic [3:0] hi; logic [3:0] lo; } byte_t;
  byte_t b, c;
  assign b = sw[7:0];
  assign c = '{hi: b.lo, lo: b.hi};        // named assignment pattern
  assign led[7:0] = c;
  assign led[15:8] = '{default: 1'b0};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h00A5; #1
    if (!(led === 16'h005A)) begin $display("FAIL: '{hi:, lo:} and '{default:} (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: typedef struct packed, nested, member read and write
next: a packed array of structs indexed by a signal, then a member select: cars[sw[15]].x