SystemVerilog probes · 12cVivado: supported

a packed array of structs indexed by a signal, then a member select: cars[sw[15]].x

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Structures', 'Packed arrays', 'Indexing and slicing of arrays': Supported; (p.287): 'Member selects: Supported'

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 8 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/12c_struct_array_var_index.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  typedef struct packed { logic [3:0] x, y; } car_t;
  car_t [1:0] cars;                                          // two cars, one packed array of structs
  assign cars = sw;
  assign led = {8'd0, cars[sw[15]].y, cars[sw[15]].x};       // the car that sw[15] picks
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [15:0] led;
  top dut(.sw(sw), .led(led));
  integer i, bad = 0; logic [7:0] car;
  initial begin
    for (i = 0; i < 65536; i++) begin
      sw = i; #1;
      car = sw[15] ? sw[15:8] : sw[7:0];                     // x is the upper nibble of a car, y the lower
      if (led !== {8'd0, car[3:0], car[7:4]}) begin bad++; if (bad < 4) $display("FAIL: sw=%h led=%h", sw, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 65536", bad);
    $finish;
  end
endmodule

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