SystemVerilog probes · 13Vivado: supported

packed 2-D, unpacked, unpacked 2-D arrays, for (int i..) in always_comb

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Packed arrays', 'Unpacked arrays', 'Multidimensional arrays', 'Indexing and slicing of arrays': Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/13_arrays_multidim.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0][3:0] p;              // packed 2-D
  logic [3:0] u [0:3];             // unpacked
  logic [1:0] m [0:1][0:1];        // unpacked 2-D
  assign p = sw;
  always_comb begin
    for (int i = 0; i < 4; i++) u[i] = p[i] ^ 4'hF;
    m[0][0] = sw[1:0]; m[0][1] = sw[3:2]; m[1][0] = sw[5:4]; m[1][1] = sw[7:6];
  end
  assign led[3:0] = p[2];
  assign led[7:4] = u[sw[13:12]];
  assign led[9:8] = m[sw[14]][sw[15]];
  assign led[15:10] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h3A5C; #1
    if (!(led === 16'h00CA)) begin $display("FAIL: vector 1 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'hD5C9; #1
    if (!(led === 16'h0335)) begin $display("FAIL: vector 2 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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