SystemVerilog probes · 13bVivado: supported

an unpacked array as a module port: input logic [3:0] v [0:3]

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.5 '3D RAM Inference' (p.161): the single-port example rams_sp_3d.sv declares 'input [A_WID-1:0] addr [NUM_RAMS-1:0]' and 'output reg [D_WID-1:0] dout [NUM_RAMS-1:0]'; the simple and true dual-port examples (p.162, p.164) do the same, and so does UG901 v2022.2 (p.160-162). IEEE 1800-2017 A.1.3: an ANSI port declaration takes unpacked dimensions

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 26 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/13b_unpacked_array_port.

design.sv

module sum4(input logic [3:0] v [0:3], output logic [5:0] s);   // an unpacked array as a port
  assign s = v[0] + v[1] + v[2] + v[3];
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] v [0:3];
  assign v[0] = sw[3:0]; assign v[1] = sw[7:4]; assign v[2] = sw[11:8]; assign v[3] = sw[15:12];
  sum4 u_sum (.v(v), .s(led[5:0]));
  assign led[15:6] = '0;
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {i[3:0], ~i[3:0], i[7:4], i[3:0] ^ i[7:4]}; #1
      if (!(led === {10'd0, 6'(sw[3:0] + sw[7:4] + sw[11:8] + sw[15:12])})) begin $display("FAIL: sum of four nibbles (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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