SystemVerilog probes · 04Vivado: unverified

always @(posedge clk or negedge clk) cnt <= cnt + 1;

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.5 (p.81) recognizes 'Rising or falling-edge clocks', not both on one register. Weak source only: AMD community forum and a university wiki quote '[Synth 8-91] ambiguous clock in event control' (an error)

What does the open-source chain do with it?

since #5; rtl: PASS; yosys: 'ERROR: Multiple edge sensitive events found for this signal!', then the CLI names the block and the cause: 'design.sv:3: ERROR [dual-edge]: this always block is sensitive to both edges of clk (@(posedge clk or negedge clk)), so cnt would change on every edge' and 'no flip-flop on the chip does that, and neither reader builds it.', with the fix (clock the block on one edge, always_ff @(posedge clk)); then yosys-slang: 'design.sv:4:5: error: simple if-else pattern expected in modeling an asynchronous load on a flip-flop'; no bitstream

Which error pages explain the messages?

• dual-edge: One always block clocked on posedge and negedge of the same clock; the chip's flip-flops have one clock edge.

What is the probe's code?

From test/sv/04_dual_edge.

design.sv

module top(input logic clk, output logic [15:0] led);
  logic [3:0] cnt = 4'd0;
  always @(posedge clk or negedge clk)   // both clock edges
    cnt <= cnt + 4'd1;
  assign led = {12'd0, cnt};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .led(led));
  initial begin
    #1 tick; tick; tick; #1
    if (!(led[3:0] === 4'd6)) begin $display("FAIL: 3 clock periods = 6 edges (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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