SystemVerilog probes · 03bVivado: unverified

a button used as an async 'reset' that loads cnt+1 (the button-as-clock counter)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.5 (p.81-82): asynchronous set/reset only; an async branch that reads the register itself is not described

What does the open-source chain do with it?

since #4; rtl: PASS; bit: stops, 'design.sv:3: ERROR [async-reset-nonconst]: this always_ff has an asynchronous reset (posedge clk or posedge btnU), so on btnU'

Which error pages explain the messages?

• async-reset-nonconst: In an always_ff with an asynchronous reset, the reset branch loads a register from a signal, or a signal is written outside the reset if/else; a flip-flop can only reset to a constant.

What is the probe's code?

From test/sv/03b_async_reset_selfref.

design.sv

module top(input logic clk, input logic btnU, output logic [15:0] led);
  logic [3:0] cnt = 4'd0;
  always_ff @(posedge clk or posedge btnU)   // button used as a second 'clock'
    if (btnU) cnt <= cnt + 4'd1;              // async branch depends on cnt itself
    else      cnt <= cnt;
  assign led = {12'd0, cnt};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnU(btnU), .led(led));
  initial begin
    #1 btnU = 1; #5 btnU = 0; #5 tick;
    if (!(led[3:0] === 4'd1)) begin $display("FAIL: one press = +1 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: always_ff @(posedge clk or posedge btnC) if (btnC) q <= sw[3:0]; (async load from a signal)
next: always @(posedge clk or negedge clk) cnt <= cnt + 1;