SystemVerilog probes · 03Vivado: unverified

always_ff @(posedge clk or posedge btnC) if (btnC) q <= sw[3:0]; (async load from a signal)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.5 'Flip-Flops, Registers, and Latches' (p.81-82) lists only asynchronous set/reset (FDCE, FDPE); it does not say what Vivado does with an asynchronous load of a signal

What does the open-source chain do with it?

'design.sv:3: ERROR [async-reset-nonconst]: this always_ff has an asynchronous reset (posedge clk or posedge btnC), so on btnC's edge every signal it writes must get a constant; here q is loaded from sw. yosys emulates that with FFs and a mux, so the board would not do what the simulation showed. Fix: reset to a constant, and load sw with the clock, behind an input of your own (load): if (btnC) q <= 0; else if (load) q <= sw; else q <= q + 1;' (since #5 in the one format, with the code and the fix; since #5 fix 3 the message names the reset and the loaded signal as the code spells them)

Which error pages explain the messages?

• async-reset-nonconst: In an always_ff with an asynchronous reset, the reset branch loads a register from a signal, or a signal is written outside the reset if/else; a flip-flop can only reset to a constant.

What is the probe's code?

From test/sv/03_async_reset_nonconst.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] q;
  always_ff @(posedge clk or posedge btnC)
    if (btnC) q <= sw[3:0];    // async 'reset' loads a signal, not a constant
    else      q <= q + 4'd1;
  assign led = {12'd0, q};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  initial begin
    sw = 16'h0005; btnC = 1; #1
    if (!(led[3:0] === 4'd5)) begin $display("FAIL: async load of 5 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    btnC = 0; #1 tick;
    if (!(led[3:0] === 4'd6)) begin $display("FAIL: count after load (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0009; btnC = 1; #1
    if (!(led[3:0] === 4'd9)) begin $display("FAIL: async load of 9 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    btnC = 0; #1 tick; tick;
    if (!(led[3:0] === 4'd11)) begin $display("FAIL: count after second load (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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